Open Access14‐bit 20 μW column‐level two‐step ADC for 640 × 512 IRFPA
Author(s) -
Wang Guannan,
Lu Wengao,
Zhang Luya,
Zhang Yacong,
Chen Zhongjian
Publication year - 2015
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2015.0491
Subject(s) - comparator , flash adc , successive approximation adc , dissipation , flash (photography) , 4 bit , voltage , power (physics) , electronic engineering , physics , electrical engineering , materials science , optics , engineering , cmos , quantum mechanics , thermodynamics
A column‐level two‐step analogue‐to‐digital converter (ADC) structure for infrared focal‐plane array (IRFPA) is proposed. The first step adopts a 16‐column‐shared 6‐bit flash ADC to accomplish the coarse conversion of 16 columns one by one. Owing to the staggered code and correction, a dynamic comparator is adopted in the flash ADC and the power dissipation of a flash ADC averaged to one column in period is only 0.386 μW. The second step is SAR conversion of which the cycle time is prolonged. The input voltage variation of the comparator in the charge redistribution structure is decreased to tens of millivolts; so a 1.8 V power supply is adequate in spite of 5 V V FS . The power dissipation of this comparator is reduced to 5.966 μW. Also, the lower clock frequency of the SAR logic reduces the dynamic power. A 14‐bit two‐step ADC is designed in 0.18 μm process and the equivalent power dissipation of the proposed ADC structure for one column is <20 μW.