Open AccessArea efficient floating‐point FFT butterfly architectures based on multi‐operand adders
Author(s) -
Kaivani Amir,
Ko SeokBum
Publication year - 2015
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2015.0342
Subject(s) - operand , coprocessor , fast fourier transform , floating point , adder , computer science , parallel computing , arithmetic underflow , fixed point arithmetic , arithmetic , computer hardware , latency (audio) , algorithm , mathematics , telecommunications , programming language
Hardware implementation of the fast Fourier transform (FFT) function consists of multiple consecutive arithmetic operations over complex numbers. Applying floating‐point arithmetic to FFT coprocessors leads to a wider dynamic range and allows the coprocessor to collaborate with general purpose processors via the standard floating‐point arithmetic. This offloads compute‐intensive tasks from the primary processor and overcomes floating‐point concerns such as scaling and overflow/underflow detection. The downside, however, is that floating‐point units are slower than the fixed‐point counterparts. One of the popular ways to improve the speed of floating‐point FFT units is to merge the arithmetic operations inside the butterfly units of a FFT architecture. This leads to a butterfly architecture based on multi‐operand adders. Butterfly units are designed, in two of the most recent works, using three‐operand and four‐operand adders. However, the work reported here by the present authors goes further and a butterfly architecture based on a five‐operand adder is proposed. Simulation results demonstrate that the proposed butterfly architecture is 50% smaller than the fastest previous work with about 17% latency overhead. Compared with the smallest previous work, the proposed design is 47% smaller and 8% faster.