Open AccessEnergy‐efficient capacitor‐splitting DAC scheme with high accuracy for SAR ADCs
Author(s) -
Xie Liangbo,
Su Jian,
Liu Jiaxin,
Wen Guangjun
Publication year - 2015
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2015.0008
Subject(s) - successive approximation adc , capacitor , converters , energy (signal processing) , shaping , reduction (mathematics) , voltage , electronic engineering , computer science , efficient energy use , mathematics , engineering , electrical engineering , statistics , geometry
An energy‐efficient capacitor‐splitting digital‐to‐analogue converter (DAC) scheme with high‐accuracy for successive approximation register (SAR) analogue‐to‐digital converters (ADCs) is presented. The proposed method uses a split‐capacitive‐array DAC structure and optimises the switching energy during conversion using energy‐efficient ‘up’ transition. The proposed switching scheme achieves a 96.91% switching energy reduction and a 75% area reduction compared with the conventional method. In addition, the third reference voltage ( V cm ) has no effect on the accuracy of the SAR ADC except the least significant bit, resulting in a good trade‐off between the energy‐efficiency and accuracy of the ADC.