Open Access0.0045 mm 2 15.8 µW three‐stage amplifier driving 10×‐wide (0.15–1.5 nF) capacitive loads with >50° phase margin
Author(s) -
Yan Zushu,
Mak PuiIn,
Law ManKay,
Martins Rui Paulo
Publication year - 2015
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2014.4391
Subject(s) - phase margin , electrical engineering , frequency compensation , gain–bandwidth product , capacitor , transconductance , amplifier , operational amplifier , resistor , physics , cmos , engineering , voltage , transistor
A three‐stage amplifier employing embedded capacitor‐multiplier compensation (ECMC) and active parallel compensation (APC) to enhance the area efficiency when driving nF‐range capacitive loads ( C L ) is presented. Unlike the conventional current‐buffer Miller compensation, ECMC applied to the dominant compensation path saves substantial power and area, while securing a large gain–bandwidth product. The created left‐half‐plane zero also benefits the phase margin (PM). For the APC, unlike the traditional passive parallel compensation, this work benefits from the Miller effect to avoid the area‐consuming resistor, and reduces the entailed capacitances without lowering the parasitic pole position. A multi‐path G m ‐boosting second stage enhances the effective transconductance and DC gain. With 0.0045 mm 2 of area and 15.8 µW of power, the 0.18 µm CMOS three‐stage amplifier measures 1.13 MHz unity‐gain frequency, 0.41 V/µs average slew rate and 56.2° PM at 1 nF C L . Stable responses with >50° PM are attained for a 10 × range of C L from 0.15 to 1.5 nF. The achieved figure‐of‐merit accounting for both die area and power compares favourably with the state of the art.