Open AccessCompact algorithmic time‐to‐digital converter
Author(s) -
Li Shuo,
Salthouse Christopher D.
Publication year - 2015
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2014.3998
Subject(s) - computer science , electronic engineering , time to digital converter , electrical engineering , engineering , telecommunications , jitter , clock signal
Time‐to‐digital converters (TDCs) are an important circuit block in time‐of‐flight sensors, fluorescence lifetime sensors, and self‐calibrating digital circuits. Fine‐resolution TDCs are usually built with chains of delay elements, but this architecture requires large area, conversion time, and power consumption. A novel compact TDC architecture based on the cyclic comparison algorithm is presented, which implemented and tested in the TSMC, 0.35 μm process within a 200 × 200 μm area is demonstrated that the proposed TDC achieves a conversion rate of 10 ns/bit and sub‐picosecond resolution. The measured power is 0.7 mW, taking 100 ns for each bit.