Open AccessSEU reliability evaluation of 3D ICs
Author(s) -
Li Huiyun,
Hu Xiaobo,
Shao Cuiping,
Zhou Jianbin,
Xu Guoqing
Publication year - 2015
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2014.3968
Subject(s) - reliability (semiconductor) , shallow trench isolation , integrated circuit , reliability engineering , three dimensional integrated circuit , through silicon via , electronic engineering , trench , vulnerability (computing) , single event upset , upset , stress (linguistics) , computer science , engineering , electrical engineering , materials science , mechanical engineering , physics , layer (electronics) , power (physics) , static random access memory , computer security , linguistics , philosophy , quantum mechanics , wafer , composite material
The single‐event‐upset (SEU) reliability is a concern for three‐dimensional (3D) integrated circuits (ICs), mainly due to the carrier mobility change caused by thermo‐mechanical stress from through‐silicon vias (TSVs) and the shallow trench isolation (STI). A systematic evaluation method is proposed to identify the vulnerability within 3D ICs at design time. The evaluation flow involves the TSV/STI stress‐aware mobility variation calculation, sensitive region marking, insertion of excitation signals and then the simulation of the 3D ICs. This method is able to help 3D IC designers to evaluate and enhance the SEU reliability at design time.