8b 0.9 V 300 MHz pipelined ADC using transistor healing and charge‐steering techniques

A fully integrated 0.9 V, 8b, 300 MHz pipelined analogue‐to‐digital converter (ADC) using healed transistors and charge‐steering op‐amps in 180 nm CMOS technology is presented. The proposed ADC employs the modified current‐driven bulk (CDB) method as a healing technique to reduce the threshold voltage ( V th ) of transistors in order to improve the overall performance. The fabricated ADC achieves an SFDR of 59.1 dB and an SNDR of 42.9 dB while dissipating 2.56 mW from the 0.9 V power supply. These results yield an FOMW of 74.8 fJ/conversion step and an FOMS of 150.6 dB.