Open AccessMicroprocessor‐conducted noise reduction with switched supercapacitors
Author(s) -
Davis A.K.,
Gunasekaran M.K.
Publication year - 2015
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2014.3612
Subject(s) - microprocessor , reduction (mathematics) , noise reduction , noise (video) , supercapacitor , electronic engineering , switched capacitor , computer science , electrical engineering , capacitance , computer hardware , engineering , capacitor , mathematics , voltage , artificial intelligence , electrode , physics , quantum mechanics , image (mathematics) , geometry
Microprocessors inject noise into the power distribution network (PDN). The point‐of‐load (PoL) converters are preferred for microprocessor supplies to reduce the total number of supplies. In addition, PoL helps in reducing voltage drop and power loss, and leverages the PDN impedance requirements by sending power at higher voltage and stepping down at the required location. Switched capacitor converters (SCCs) are replacing inductor‐dominated buck converters in PoL applications because of their potential to integrate with microprocessors. A new method to reduce microprocessor‐conducted noise by switched supercapacitors built with a 1:1 SCC is proposed. The high‐frequency microprocessor noise conducted into the PDN is reduced by the capacitors switching at low frequency. An analogue implementation of the individual switches with low noise coupling through parasitic capacitance and with current limiting is shown. An insertion loss of 40–20 dB in the conducted frequency range (150 kHz–30 MHz) is observed in experiments. The idea can be used as a standalone method or can be incorporated into conventional SCCs with modifications as an additional feature.