Open AccessFlexible and low‐complexity bit‐reversal scheme for serial‐data FFT processors
Author(s) -
Yu Chu
Publication year - 2015
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2014.3270
Subject(s) - fast fourier transform , bit (key) , computer science , scheme (mathematics) , electronic engineering , arithmetic , parallel computing , computer hardware , algorithm , engineering , mathematics , computer network , mathematical analysis
A simple yet flexible bit‐reversal hardware scheme applicable to variable‐length fast Fourier transform (FFT) processors to facilitate the continuous flow of serial data is presented. The proposed design employs a length‐ N two‐port register file ( N is the processing size of the FFT), and a simple address generator to perform variable‐length bit‐reversal operations on the input or output of the FFT processor. This enables the conversion of bit‐reversed data to the natural order. The proposed scheme is superior to the existing technologies because of its ability to process a continuous‐flow input sequence and its applicability to variable‐length FFT processors without the need for a shuffling mechanism on the input and output memory ports. The proposed design is particularly suitable for applications involving bit‐reversal operations on large‐point FFT processors.