Open Access2.56 GHz sub‐harmonically injection‐locked PLL with cascaded DLL for multi‐phase injection
Author(s) -
Choi Changsung,
Hwang Sewook,
Song Junyoung,
Kim Chulwoo
Publication year - 2014
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2014.3191
Subject(s) - phase noise , dbc , phase locked loop , voltage controlled oscillator , injection locking , cmos , pll multibit , delay locked loop , offset (computer science) , electronic engineering , materials science , physics , voltage , electrical engineering , computer science , engineering , optics , laser , programming language
A 2.56 GHz injection‐locked phase‐locked loop (ILPLL) cascaded with a delay‐locked loop (DLL) for minimising phase noise is presented. Generally, an ILPLL includes an injection‐locked voltage‐controlled oscillator (ILVCO), which is directly injected with the reference clock phase. However, the proposed scheme connects the output multi‐phased clocks of the DLL to the injection node and they can be selected with turn on/off switches. This can shorten the realignment time of the VCO phases and thus the in‐band phase noise is decreased. The proposed circuit is implemented in a 65 nm CMOS technology, and reduces the phase noise by 10.86 dBc/Hz at a 1 MHz offset with 16 multi‐phased injections, compared with a conventional PLL.