Open AccessCluster‐error correction for through‐silicon vias in 3D ICs
Author(s) -
Huang TsungChu
Publication year - 2015
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2014.3151
Subject(s) - error detection and correction , interconnection , computer science , silicon , cluster (spacecraft) , algorithm , scheme (mathematics) , parity bit , electronic engineering , mathematics , physics , engineering , optoelectronics , telecommunications , mathematical analysis , programming language
The two‐dimensional parity check is the optimum single‐error‐correction code in terms of speed. In this reported work it is employed to develop two sliding schemes for through‐silicon‐via cluster error correction in three‐dimensional ICs. For k bits of source data, the one‐dimensional sliding scheme can correct a single cluster error up to about √ k bits and more extra discrete errors can be corrected by the two‐dimensional sliding scheme. Experiments show that for several hundreds of through‐silicon vias (TSVs), two trees of 3‐level 2‐input exclusive‐OR (XOR) gates are almost optimised to encode and decode each interconnect, and the time penalty can be controlled within about 1 ns.