Open AccessTwo‐stage hot‐carrier‐induced degradation of p‐type LDMOS transistors
Author(s) -
Chen Jone F.,
Chen TzuHsiang,
Ai DengRen
Publication year - 2014
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2014.2901
Subject(s) - ldmos , materials science , optoelectronics , transistor , stress (linguistics) , degradation (telecommunications) , current (fluid) , fabrication , voltage , semiconductor , trapping , mosfet , electrical engineering , engineering , linguistics , philosophy , medicine , ecology , alternative medicine , pathology , biology
Hot‐carrier‐induced device degradation of high‐voltage p‐type lateral diffused metal–oxide semiconductor (LDMOS) transistors is investigated. A two‐stage linear region drain current ( I Dlin ) shift ( I Dlin shift increases rapidly at the beginning of stress but tends to saturate when the stress time is longer) is observed. Technology computer‐aided‐design simulations and direct current current–voltage measurement results suggest that the decrease of residual fabrication interface traps ( N IT ) leads to an initial increase in I Dlin shift. On the other hand, two competing mechanisms, i.e. increase in N IT generation and increase in electron trapping, are responsible for the saturated I Dlin shift when the stress time is longer.