Open AccessSub‐threshold SRAM bit cell pnn for VDD min and power reduction
Author(s) -
Chien Y.C.,
Chiang I.H.,
Wang J.S.
Publication year - 2014
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2014.2357
Subject(s) - reduction (mathematics) , static random access memory , power (physics) , bit (key) , computer science , electronic engineering , computer network , computer hardware , engineering , mathematics , physics , geometry , quantum mechanics
The bit cell is a key component that determines the VDD min and power consumption of a sub‐threshold static random access memory (SRAM). A new bit cell with a pnn ‐type latch structure is proposed. The analysis and measurement results indicate that the pnn bit cell outperforms the conventional bit cells in terms of VDD min and power reduction.