Open AccessImproved binary‐weighted split‐capacitive‐array DAC for high‐resolution SAR ADCs
Author(s) -
Li Y.,
Lian Y.
Publication year - 2014
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2014.1752
Subject(s) - least significant bit , capacitive sensing , integral nonlinearity , capacitor , successive approximation adc , capacitance , linearity , computer science , electronic engineering , differential nonlinearity , binary number , converters , electrical engineering , mathematics , engineering , physics , voltage , arithmetic , electrode , quantum mechanics , operating system
An improved split‐capacitive‐array digital‐to‐analogue converter (DAC) with an optimised segmentation degree (i.e. the number of bits in the most significant bit (MSB) sub‐array) is proposed to reduce the area, the switching power consumption and improve the linearity compared to a conventional binary‐weighted (CBW) capacitive‐array DAC and a conventional binary‐weighted split‐capacitive‐array with an attenuation capacitor (BWA) DAC. The presented analysis considers the area and the power dissipation from the DAC as well as the analogue‐to‐digital converter's (ADC's) dynamic performance to determine the optimum segmentation degree for the proposed split‐capacitive‐array DAC and the BWA DAC. Using the minimum matching requirement for the unit capacitor in a 12‐bit CBW DAC, the proposed split‐capacitive‐array DAC with an MSB:LSB = 8:4 segmentation reduces the input capacitance by 2× and reduces the switching power by 15× compared to the 12‐bit CBW DAC. It also improves the ADC's dynamic performance and reduces the switching power by 3.75× compared to the conventional 12‐bit BWA DAC with an MSB:LSB = 10:2 segmentation.