Open AccessDesign for security test against fault injection attacks
Author(s) -
Shao Cuiping,
Li Huiyun,
Xu Guoqing,
Xiong Liying
Publication year - 2014
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2014.1666
Subject(s) - fault injection , chinese remainder theorem , computer science , scan chain , overhead (engineering) , fault coverage , embedded system , cryptography , fault (geology) , transient (computer programming) , key (lock) , reliability engineering , computer security , integrated circuit , electronic circuit , algorithm , engineering , software , electrical engineering , seismology , geology , programming language , operating system
A design‐for‐test method on cryptographic integrated circuits against fault injection attacks is proposed. The method involves identifying the sensitive registers, inserting the scan chain accordingly and functioning in test mode during the fault injection security test. The transient errors caused by fault injection can be quickly and efficiently revealed for security evaluation, but the errors cannot be exploited by the attackers to compromise the secret keys, due to isolation of the secret key related registers. The experimental result on a Chinese remainder theorem‐RSA implementation verifies the feasibility of the proposed method with the area overhead as low as 2.5%. The method is able to facilitate a fast and volume test.