Open AccessEnergy‐efficient static sparse‐tree adder based on MUX‐less bypassing architecture
Author(s) -
Choi Seongrim,
Ahn Jonghun,
Byun Kyungjin,
Nam ByeongGyu
Publication year - 2014
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2014.1639
Subject(s) - adder , multiplexer , computer science , tree (set theory) , architecture , energy (signal processing) , electronic engineering , efficient energy use , computer architecture , engineering , electrical engineering , telecommunications , multiplexing , mathematics , cmos , mathematical analysis , art , statistics , visual arts
An energy‐efficient 64 bit static sparse‐tree adder using a multiplexer (MUX)‐less bypassing scheme is proposed for mobile central processing units. Conventionally, bypassing schemes have been used to eliminate unnecessary switching of circuits but have incorporated a large delay overhead due to their output MUX, which reduces the energy efficiency of circuits in terms of power‐delay product (PDP). A novel static sparse‐tree adder is presented based on a proposed MUX‐less bypassing scheme to reduce the delay associated with the conventional bypassing scheme, thereby improving the energy efficiency, i.e. the PDP. Simulation results show a 30% reduction in PDP compared to the conventional bypassing adder and a 13% reduction from the state‐of‐the‐art technique.