
Area‐efficient method to approximate two minima for LDPC decoders
Author(s) -
Jung Jaehwan,
Lee Youngjoo,
Park InCheol
Publication year - 2014
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2014.1549
Subject(s) - maxima and minima , multiplexer , low density parity check code , comparator , simple (philosophy) , computer science , algorithm , decoding methods , parallel computing , mathematics , multiplexing , telecommunications , engineering , electrical engineering , voltage , mathematical analysis , philosophy , epistemology
A simple yet effective method is proposed to reduce the hardware complexity of min‐sum‐based low‐density parity‐check (LDPC) decoders. The proposed method finds the second minimum from the last four candidates of the first minimum, and can be implemented with only a few hardware components. In the case of 64 inputs, the proposed method reduces the comparators and 2‐to‐1 multiplexers by 48 and 64% compared to the conventional method that finds two exact minima.