Open AccessCompact diamond MOSFET model accounting for PAMDLE applicable down 150 nm node
Author(s) -
Gimenez S.P.,
Davini E.,
Peruzzi V.V.,
Renaux C.,
Flandre D.
Publication year - 2014
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2014.1229
Subject(s) - mosfet , silicon on insulator , diamond , node (physics) , materials science , planar , optoelectronics , short channel effect , transistor , field effect transistor , figure of merit , channel (broadcasting) , electronic engineering , silicon , electrical engineering , computer science , engineering , voltage , computer graphics (images) , structural engineering , composite material
The performance improvements for integrated circuit applications of silicon‐on‐insulator (SOI) metal–oxide semiconductor field‐effect transistors (MOSFETs) implemented with diamond layout style (hexagonal gate geometry) are quantified, thanks to the longitudinal corner effect and parallel association of MOSFETs with different channel lengths effect contributions. Futhermore, an accurate analytical drain current model for planar diamond SOI MOSFET for micrometre scale effective channel lengths is proposed and validated. The concept is then extended by 3D simulations for the 150 nm node fully‐depleted SOI n ‐channel MOSFETs.