Open AccessConstant twiddle factor multiplier sharing in multipath delay feedback parallel pipelined FFT processors
Author(s) -
Yang SeungWon,
Lee JongYeol
Publication year - 2014
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2014.1186
Subject(s) - twiddle factor , fast fourier transform , multiplier (economics) , parallel computing , mathematics , computer science , arithmetic , algorithm , fourier transform , fourier analysis , mathematical analysis , short time fourier transform , economics , macroeconomics
A new constant twiddle factor multiplier sharing method in parallel pipelined fast Fourier transform (FFT) processors based on a multi‐path delay feedback architecture which consists of multiple single‐path delay feedback datapaths is presented. The proposed method exploits constant twiddle factor multiplier relocation which moves a constant twiddle factor multiplier into a feedback path based on twiddle factor decomposition. By relocating a twiddle factor multiplier, the timing of twiddle factor multiplications is changed so that the multiplications with a twiddle factor are performed at different clock cycles in two datapaths, which makes it possible that the two datapaths share a multiplier operating with the twiddle factor. A reduction of 50% in the number of constant twiddle factor multipliers in the first two stages of a 128‐point four‐parallel pipelined FFT processor is achieved using the proposed method.