Open Access2 GHz sub‐harmonically injection‐locked PLL with mixer‐based injection timing control in 0.18 µm CMOS technology
Author(s) -
Huang Ke,
Wang Ziqiang,
Zheng Xuqiang,
Zhang Chun,
Wang Zhihua
Publication year - 2014
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2014.0825
Subject(s) - dbc , phase locked loop , cmos , jitter , phase noise , offset (computer science) , materials science , injection locking , frequency offset , electrical engineering , electronic engineering , optoelectronics , engineering , physics , computer science , optics , laser , orthogonal frequency division multiplexing , programming language , channel (broadcasting)
A 2 GHz sub‐harmonically injection‐locked phase‐locked loop (SILPLL) with a self‐aligned injection window is presented. The SILPLL adopts a mixer‐based self‐align technique to automatically adjust the injection timing, overcoming the speed limitation of the phase detection. Circuit techniques such as a symmetrical mixer and a V/I converter with mismatch cancellation are adopted to improve injection timing accuracy. Fabricated in a 180 nm CMOS technology, the SILPLL exhibits −127 dBc/Hz phase noise at 1 MHz offset and draws 6.9 mA current from a 1.8 V power supply. The measured root‐mean‐square jitter integrating from 1 kHz to 40 MHz is 214 fs and the reference spur is −61 dBc.