Open AccessLUT‐oriented dual‐rail quasi‐delay‐insensitive logic synthesis
Author(s) -
Lemberski I.
Publication year - 2014
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2014.0242
Subject(s) - lookup table , dual (grammatical number) , logic synthesis , computer science , logic gate , logic optimization , electronic engineering , arithmetic , algorithm , mathematics , engineering , programming language , art , literature
The method of quasi‐delay‐insensitive logic synthesis using look‐up tables (LUTs) is described. It is shown that the dual‐rail sum‐of‐minterm function hazard‐free implementation can be done using a single LUT. Namely, instead of the conventional approach based on a DIMS representation where each minterm is implemented on a C‐element, the whole sum‐of‐minterm function is mapped into the single C‐element. For Boolean network implementation, it is proved that a fork with branches to different nodes is not required to be isochronic. It simplifies technological synthesis and allows using existing placement and routine methods and tools supposed for synchronous logic. Compared to the conventional approach, the method reduces significantly circuit complexity (in terms of the number of LUTs).