Open Access1–5 GHz duty‐cycle corrector circuit with wide correction range and high precision
Author(s) -
Qiu Yusong,
Zeng Yun,
Zhang Feng
Publication year - 2014
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2014.0170
Subject(s) - duty cycle , jitter , cmos , amplifier , voltage , robustness (evolution) , electronic engineering , electrical engineering , engineering , control theory (sociology) , computer science , biochemistry , chemistry , control (management) , artificial intelligence , gene
An all‐analogue feedback duty‐cycle corrector (DCC) circuit with high precision and frequency is presented to tighten duty cycle into an allowable range and compensate for duty‐cycle uncertainties in high‐speed interfaces. The proposed DCC is employed to calibrate the duty cycle of the clock to reduce the deterministic jitter introduced by the duty‐cycle distortion. It extracts the duty‐cycle information by a differential duty amplifier detection scheme and corrects the clock distortion by a duty‐cycle adjuster through the negative feedback loop. The DCC has improved robustness, correction range and operating frequency as compared with other DCCs. With post‐simulated results using 55 nm CMOS technology, the output duty cycle is corrected to 50 ± 0.1% over the input duty‐cycle range of 20–80% for 1–5 GHz. It consumes 3.6 mW at 3 GHz using a 1.2 V supply voltage and occupies an area of only 0.00174 mm 2 .