Open AccessMetastability occurrence based physical unclonable functions for FPGAs
Author(s) -
Wieczorek P.Z.,
Golofit K.
Publication year - 2014
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2014.0143
Subject(s) - physical unclonable function , field programmable gate array , digital clock manager , metastability , computer science , randomness , gate array , electronic circuit , cryptography , electronic engineering , computer hardware , clock signal , engineering , clock skew , electrical engineering , physics , algorithm , mathematics , statistics , quantum mechanics
A novel concept of a physical obfuscation of cryptographic keys is introduced which basically utilises identification of the metastable behaviour of field programmable gate array (FPGA) flip‐flops, i.e. the time variability of the metastability's appearance. Clock and data intervals leading to metastability ( δ ) are measured with the use of programmable delay lines available in digital clock managers (DCMs). The DCM acts as a variable clock phase regulator, whereas another circuit detects metastable events. The parts of binary words representing δ become segments of a physical unclonable function key. Preliminary results show significant differences in interval δ values when a slight change in circuit implementation occurs (in placement, node connections, surrounding sub‐circuits etc.). Similar FPGA devices manufactured in the same process having an identical structure also behave significantly differently due to the intrinsic inter‐class randomness.