Metastability occurrence based physical unclonable functions for FPGAs

A novel concept of a physical obfuscation of cryptographic keys is introduced which basically utilises identification of the metastable behaviour of field programmable gate array (FPGA) flip‐flops, i.e. the time variability of the metastability's appearance. Clock and data intervals leading to metastability ( δ ) are measured with the use of programmable delay lines available in digital clock managers (DCMs). The DCM acts as a variable clock phase regulator, whereas another circuit detects metastable events. The parts of binary words representing δ become segments of a physical unclonable function key. Preliminary results show significant differences in interval δ values when a slight change in circuit implementation occurs (in placement, node connections, surrounding sub‐circuits etc.). Similar FPGA devices manufactured in the same process having an identical structure also behave significantly differently due to the intrinsic inter‐class randomness.