Open AccessNanopore‐application CMOS potentiostat design with input parasitic compensation
Author(s) -
Kim Jungsuk,
Dunbar W.B.
Publication year - 2014
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2014.0049
Subject(s) - potentiostat , cascode , nanopore , cmos , electronic engineering , parasitic capacitance , bandwidth (computing) , amplifier , capacitance , electrical engineering , capacitor , engineering , computer science , materials science , nanotechnology , voltage , physics , electrode , telecommunications , quantum mechanics , electrochemistry
A low‐noise area‐efficient potentiostat design for nanopore applications is presented. By adopting a cascode amplifier and a Wilson current mirror, the input resistance is drastically decreased, which enables one to obtain a desirable bandwidth to detect DNA translocation events in nanopore sensors. A novel compensation technique is also proposed to relieve a deleterious effect by the input parasitic capacitances.