Ultra‐low power design strategy for two‐stage amplifier topologies | Zendy

Leene L.B. | Zendy; Constandinou T.G. | Zendy

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Ultra‐low power design strategy for two‐stage amplifier topologies

Author(s) -

Leene L.B.,

Constandinou T.G.

Publication year - 2014

Publication title -

electronics letters

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.375

H-Index - 146

ISSN - 1350-911X

DOI - 10.1049/el.2013.4196

Subject(s) - network topology , stage (stratigraphy) , amplifier , power (physics) , electronic engineering , computer science , engineering , topology (electrical circuits) , electrical engineering , physics , computer network , cmos , paleontology , quantum mechanics , biology

A novel two‐stage amplifier topology and ultra‐low power design strategy for two‐stage amplifiers that utilises pole zero cancellation to address the additional power requirements for stability are presented. For a 288 nA total bias, the presented amplifier achieves a 1.07 MHz unity gain frequency with a 8560 pF MHz/mA figure of merit.

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