Open AccessSwitching architecture for CMOS exponential function generators eliminating squarer/multiplier circuits
Author(s) -
Ray S.,
Hella M.M.
Publication year - 2014
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2013.3988
Subject(s) - cmos , multiplier (economics) , exponential function , transistor , electronic engineering , electronic circuit , computer science , electrical engineering , mathematics , engineering , voltage , mathematical analysis , economics , macroeconomics
A switching architecture for exponential function generators in submicron CMOS technology is proposed. The architecture is based on second‐order rational approximation of exponential functions and can be realised using MOS transistors in the saturation regime. An implementation eliminating complex squarer/multiplier circuits is presented in 0.13 μm CMOS technology. Simulation results show a dB‐linear range of 46 dB with less than ± 0.5 dB linear error while dissipating a maximum of 0.45 mW from a 1.2 V power supply.