Open Access6.8 mW 15 dBm IIP3 CMOS common‐gate LNA employing post‐linearisation technique
Author(s) -
Guo Benqing,
Wen Guangjun,
An Shiquan
Publication year - 2014
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2013.3442
Subject(s) - pmos logic , cmos , common gate , amplifier , electrical engineering , linearity , transistor , noise figure , electronic engineering , low noise amplifier , physics , engineering , voltage
A linearised differential common‐gate CMOS low‐noise amplifier (LNA) is proposed. The linearity is improved by a cross‐coupled post‐distortion technique, employing PMOS in a weak inversion region as an auxiliary field effect transistor to cancel the third‐order nonlinear currents of a common‐gate LNA and impair the related second‐order nonlinear currents. Meanwhile, the resulting noise figure is little affected. The LNA implemented in a 0.18 μm CMOS technology demonstrates that IIP3 and gain have about 8.2 and 1.5 dB improvements in the designed frequency band, respectively. A NF of 3.4 dB is obtained with a power dissipation of 6.8 mW under a 1.8 V power supply.