Open AccessScalable and parameterised VLSI architecture for efficient sparse approximation in FPGAs and SoCs
Author(s) -
Ren F.,
Xu W.,
Marković D.
Publication year - 2013
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2013.2978
Subject(s) - field programmable gate array , scalability , computer science , very large scale integration , computer architecture , flexibility (engineering) , gate array , system on a chip , throughput , embedded system , computer engineering , computer hardware , telecommunications , statistics , mathematics , database , wireless
A parameterised and scalable very large scale integration (VLSI) soft intellectual property (IP) is presented that can be implemented in programmable logic devices, such as field programmable gate arrays (FPGAs) or a system‐on‐chip design for efficient sparse approximation. The proposed architecture is optimised based on the orthogonal matching pursuit algorithm by both algorithm reformulation and architecture resource sharing techniques. The soft IP core supports a floating‐point data format with 10 design parameters, which provides the necessary flexibility for application‐specific customisation. The soft IP is evaluated on various FPGA platforms. The evaluation results show that design can achieve up to 30% higher throughput than the existing solutions while offering a larger dynamic range capability and better design flexibility.