Open AccessProgrammable fractional‐ratio frequency multiplying clock generator
Author(s) -
Han Sangwoo,
Kim Jintae,
Kim Jongsun
Publication year - 2014
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2013.2857
Subject(s) - jitter , clock generator , multiplication (music) , cpu multiplier , clock rate , generator (circuit theory) , cmos , electronic engineering , clock skew , computer science , physics , clock signal , engineering , power (physics) , acoustics , quantum mechanics
A new programmable delay‐locked loop (DLL) based fractional frequency multiplying clock generator is presented. In contrast to conventional DLL‐based clock generators that generate only integer clock multiplication, the proposed clock generator provides fractional‐ratio frequency multiplication while maintaining the advantages of DLLs, such as the deskewing between the input and the output clocks. Implemented in a 0.13 µm 1.2 V CMOS process, the proposed clock generator achieves an effective peak‐to‐peak jitter of 7.5 ps and occupies an active area of 0.018 mm 2 while dissipating 9.0 mW at 1.5 GHz. The output frequency ranges from 0.85 to 1.5 GHz with programmable fractional multiplication ratios of N / M , where N = 4, 5, 8, 10 and M = 1, 2, 3.