
Efficient encoding of QC‐LDPC codes with multiple‐diagonal parity‐check structure
Author(s) -
Zhang Peng,
Yu Shuo,
Liu Changyin,
Jiang Lanxiang
Publication year - 2014
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2013.2390
Subject(s) - low density parity check code , encoder , computer science , adder , accumulator (cryptography) , diagonal , arithmetic , parity (physics) , parity bit , shift register , encoding (memory) , parity check matrix , algorithm , parallel computing , theoretical computer science , mathematics , decoding methods , telecommunications , physics , chip , geometry , particle physics , artificial intelligence , operating system , latency (audio)
An efficient encoding method is proposed for a class of quasi‐cyclic low‐density parity‐check (QC‐LDPC) codes with a multiple‐diagonal parity‐check structure. Its easy implementation with Chinese digital terrestrial/television multimedia broadcasting standard as an example is discussed. It is shown that the proposed encoder runs significantly faster and requires much fewer resources than the conventional shift‐register–adder–accumulator encoder.