Open AccessHigh reliability sensing circuit for deep submicron spin transfer torque magnetic random access memory
Author(s) -
Kang Wang,
Zhao Weisheng,
Klein J.O.,
Zhang Youguang,
Chappert C.,
Ravelosona D.
Publication year - 2013
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2013.2319
Subject(s) - spin transfer torque , offset (computer science) , reliability (semiconductor) , tunnel magnetoresistance , cmos , monte carlo method , voltage , magnetoresistive random access memory , electronic engineering , random access , torque , random access memory , electrical engineering , electronic circuit , integrated circuit , computer science , engineering , materials science , physics , computer hardware , magnetic field , power (physics) , magnetization , quantum mechanics , thermodynamics , mathematics , composite material , operating system , layer (electronics) , programming language , statistics
A high reliability offset‐tolerant sensing circuit is presented for deep submicron spin transfer torque magnetic tunnel junction (STT‐MTJ) memory. This circuit, using a triple‐stage sensing operation, is able to tolerate the increased process variations as technology scales down to the deep submicron nodes, thus improving significantly the sensing margin. Meanwhile, it clamps the bit‐line voltage to a predefined small bias voltage to avoid any read disturbance during the sensing operations. By using the STMicroelectronics CMOS 40 nm design kit and a precise STT‐MTJ compact model, Monte Carlo simulations have been carried out to evaluate its sensing performance.