Open AccessContinuous‐flow variable‐length memoryless linear regression architecture
Author(s) -
Garrido M.,
Grajal J.
Publication year - 2013
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2013.2106
Subject(s) - linear regression , variable (mathematics) , computer science , process (computing) , regression , adder , algorithm , mathematics , statistics , machine learning , telecommunications , mathematical analysis , latency (audio) , operating system
A pipelined circuit to calculate linear regression is presented. The proposed circuit has the advantages that it can process a continuous flow of data, it does not need memory to store the input samples and supports variable length that can be reconfigured in run time. The circuit is efficient in area, as it consists of a small number of adders, multipliers and dividers. These features make it very suitable for real‐time applications, as well as for calculating the linear regression of a large number of samples.