Open AccessSoftware tool for efficient FPGA design of direct data domain approach for space‐time adaptive processing
Author(s) -
Jarrah A.,
Jamali M.
Publication year - 2013
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2013.1307
Subject(s) - field programmable gate array , computer science , software , embedded system , computer architecture , domain (mathematical analysis) , data processing , computer hardware , computer engineering , computational science , real time computing , programming language , operating system , mathematics , mathematical analysis
Space‐time adaptive processing algorithms have been proven to be a very effective way to mitigate the effects of multipath and interference. Due to the fast‐changing clutter scenario, the stationary property of the data is destroyed and fails if the interference scenario ever becomes heterogeneous. Direct data domain (D 3 ) methods can accommodate non‐stationary data and can effectively suppress the clutter. However, the computation of D 3 is very intensive. It is desirable to implement the D 3 algorithm on a FPGA architecture for real‐time applications. FPGAs can accommodate parallel and pipelined architecture. Here, the first FPGA design for the D 3 algorithm and a new software package are presented. The software tool is capable of auto‐generating a fully optimised VHDL representation of D 3 and provides various performance parameters. The tool can be used by the designer to develop an overall system on chip (SoC) by using various constraints and options to meet certain performance criteria. Experimental results demonstrate that the authors' hardware version of the D 3 algorithm can significantly outperform an equivalent software version.