Open Access0.0012 mm 2 , 8 mW, single‐to‐differential converter with < 1.1% data cross error and < 3.4 ps RMS jitter up to 14 Gbit/s data rate
Author(s) -
Chen Yong,
Mak PuiIn,
Zhang Li,
Qian He,
Wang Yan
Publication year - 2013
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2013.0992
Subject(s) - jitter , wireline , single stage , inductor , cmos , physics , gigabit , differential (mechanical device) , bandwidth (computing) , topology (electrical circuits) , electronic engineering , control theory (sociology) , computer science , voltage , electrical engineering , engineering , optoelectronics , wireless , optics , telecommunications , thermodynamics , control (management) , artificial intelligence , aerospace engineering
An extremely compact, doubly balancing single‐to‐differential converter (S2D) for high‐speed wireline systems is reported. It incorporates a two‐stage topology with ‘coarse balancing’ in the first stage and ‘fine balancing’ in the second stage by adopting a compact ‘positive‐feedback active inductor’ that simultaneously boosts the signal bandwidth. Fabricated in 65 nm CMOS, the S2D measures < 1.1% data cross error and < 3.4 ps RMS jitter up to a 14 Gbit/s data rate. The die occupies 0.0012 mm 2 and consumes 8 mW.