Open AccessDesign of integer motion estimator of HEVC for asymmetric motion‐partitioning mode and 4K‐UHD
Author(s) -
Byun J.,
Jung Y.,
Kim J.
Publication year - 2013
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2013.0936
Subject(s) - estimator , computer science , mode (computer interface) , motion estimation , motion (physics) , integer (computer science) , algorithm , mathematics , computer vision , statistics , programming language , operating system
A design for an integer motion estimator of high‐efficiency video coding (HEVC) is presented. HEVC supports the 64 × 64 coding tree unit, the recursive quad‐tree coding unit structure and the asymmetric motion‐partitioning mode in a high compression ratio. These features require a structure of integer motion estimation that is more complex than that of H.264/AVC. The new structures of a memory read controller and a sum of absolute difference (SAD) summation block are proposed. The new memory read controller reduces the internal memory read time, and the new SAD summation block structure supports the recursive quad‐tree coding unit structure and the asymmetric motion‐partitioning mode. The proposed design is implemented in Verilog HDL and synthesised using the 65 nm CMOS technology. The gate count is 3.56 M, and the internal static random access memory is about 20 kbyte. The operation frequency is 250 MHz when a 4 K‐Ultra high definition (UHD) (3840 × 2160P at 30 Hz) sized video is encoded.