Open AccessLow‐power high‐speed full adder for portable electronic applications
Author(s) -
Tung C.K.,
Shieh S.H.,
Cheng C.H.
Publication year - 2013
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2013.0893
Subject(s) - adder , cmos , transistor , computer science , power (physics) , electronic engineering , reduction (mathematics) , electrical engineering , engineering , mathematics , voltage , physics , quantum mechanics , geometry
A low‐power, high‐speed full adder (FA), abbreviated as LPHS‐FA, is presented as an elegant way to reduce circuit complexity and improve the performance thereof. Employing as few as 15 MOSFETs in total, an LPHS‐FA requires 60–73% fewer transistors than other existing FAs with drivability. For validation purpose, HSPICE simulations are conducted on all the proposed and referenced FAs based on the TSMC 0.18‐μm CMOS process technology. The LPHS‐FA is found to provide a 20.4–21.2% power saving, a 12.3–67.0% delay time reduction and a 35–102% reduction in power delay product compared with the referenced FAs. In short, an LPHS‐FA is presented in a concise form as a high‐performance FA in practical applications.