Comparing techniques for spur reduction in digital bang‐bang PLLs | Zendy

Maffezzoni P. | Zendy; Marucci G. | Zendy; Levantino S. | Zendy; Samori C. | Zendy

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Comparing techniques for spur reduction in digital bang‐bang PLLs

Author(s) -

Maffezzoni P.,

Marucci G.,

Levantino S.,

Samori C.

Publication year - 2013

Publication title -

electronics letters

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.375

H-Index - 146

eISSN - 1350-911X

pISSN - 0013-5194

DOI - 10.1049/el.2012.4402

Subject(s) - spur , reduction (mathematics) , electronic engineering , computer science , phase locked loop , control theory (sociology) , engineering , mathematics , jitter , control (management) , artificial intelligence , geometry , structural engineering

Bang‐bang phase‐locked loops (PLLs) are prone to generate unwanted output spur tones and high noise floor. In this reported work, a spur reduction technique based on dithering is compared to an alternative technique which exploits oscillator intrinsic noise. It is shown how the latter, joined to a proper loop design, allows eliminating unwanted spur tones while yielding a lower noise floor.

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