Open AccessEfficient encoding of QC‐LDPC codes based on rotate‐left‐accumulator circuits
Author(s) -
Zhang Peng,
Liu Changyin,
Jiang Lanxiang
Publication year - 2013
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2012.4342
Subject(s) - accumulator (cryptography) , low density parity check code , computer science , electronic circuit , encoding (memory) , forward error correction , error floor , arithmetic , algorithm , decoding methods , theoretical computer science , mathematics , electrical engineering , engineering , artificial intelligence
For efficient hardware implementation of QC‐LDPC encoders, four types of rotate‐left‐accumulator (RLA) circuits are proposed. Although the performance of a type I RLA circuit is exactly identical to the most widely used shift‐register‐adder‐accumulator (SRAA) circuit, its reasonable structure can derive the other three counterparts. Both type II and III RLA circuits are highly area efficient, and have the same speed as the SRAA circuit. Compared with these serial‐in circuits, the parallel‐in type IV RLA circuit is faster at the cost of more memory, and suitable for applications where generator matrices have fewer block rows or special parity‐check matrices are used to encode.