Open AccessWide‐range (25 ns) and high‐resolution (48.8 ps) clock phase shifter
Author(s) -
Wu Guoying,
Yu Bryan,
Gui Ping,
Moreira P.
Publication year - 2013
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2012.4274
Subject(s) - cmos , resolution (logic) , linearity , materials science , phase shift module , phase locked loop , electronic engineering , phase (matter) , power consumption , range (aeronautics) , high resolution , power (physics) , optoelectronics , optics , physics , jitter , computer science , engineering , insertion loss , remote sensing , quantum mechanics , artificial intelligence , composite material , geology
A wide‐range (25 ns), high‐resolution (48.8 ps) clock phase shifter developed and fabricated using a 0.13 µm CMOS technology is presented. To achieve both wide range and high resolution with good linearity while minimising area and power consumption, a coarse–fine two‐step phase‐shifting structure is proposed. A delay‐locked loop with an unconventional clock input setup is used in the fine‐shifting stage to ahieve the high resolution. Test results show that the standard deviations of the differential nonlinearity and integral nonlinearity are 4.7 ps and 4.3 ps, respectively.