Open AccessHardware‐efficient phase‐detection technique for digital clock and data recovery
Author(s) -
ZargaranYazd A.,
Keikhosravy K.,
Rashtian H.,
Mirabbasi S.
Publication year - 2013
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2012.3722
Subject(s) - comparator , gigabit , computer science , cmos , phase detector , sampling (signal processing) , chip , data recovery , electronic engineering , computer hardware , phase locked loop , clock recovery , phase (matter) , clock signal , electrical engineering , engineering , jitter , detector , telecommunications , voltage , physics , quantum mechanics
A phase‐detection technique for digital clock and data recovery (CDR) in multi‐Gbit/s serial links is presented. Compared to conventional sampling‐based receivers, hardware efficiency at the system‐level is achieved by extracting timing information from analysing the occurrence of certain patterns at the output of four comparators. The arrangement of the decision threshold and sampling time of these comparators is discussed, and the phase and frequency detection characteristic of such an arrangement is evaluated. The technique is validated through a proof‐of‐concept 12.5 Gbit/s CDR chip that is fabricated in 90nm CMOS.