Open AccessHysteresis settling technique for CMOS comparators based on substrate voltage
Author(s) -
Rodrigues C.R.,
Muller C.,
Neto D.J. Monteiro
Publication year - 2013
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2012.3191
Subject(s) - comparator , cmos , hysteresis , settling , settling time , materials science , substrate (aquarium) , voltage , electronic engineering , optoelectronics , electrical engineering , computer science , engineering , physics , control engineering , step response , geology , oceanography , quantum mechanics , environmental engineering
A hysteresis is a widely employed solution to mitigate the effect of noise on comparators. Presented is a very simple technique, applicable to any topology of MOS differential comparator. It consists of imposing different bulk‐source voltage to the input MOS differential pair. Depending on the polarity of the input signal, one substrate is connected to the rail voltage and the other to a reference control voltage. So, when the slope inverts the connections are switched through pMOS switches. Simulation results show that the hysteresis up to 302,6 mV can be linearly controlled for bulk voltages ranging from 0 to 500 mV, for XFAB 0.35XH technology. Finally, an aproximation for the control rule is proposed.