Hardware thread‐context switching

Numerous proposals have advanced fine‐grained thread migration as a mechanism to address power, performance, reliability and memory coherence problems. However, exploiting conventional context switch mechanisms carries significant overhead, limiting the granularity of thread movement. Proposed is a novel hardware context switching circuit that enables low‐overhead hardware thread migration between cores in a single‐chip multiprocessor. This switching circuit supports multiple simultaneous thread switches and can store the context of both currently running and time‐multiplexed threads. The circuit drastically reduces the direct cost of context switches.