Open AccessUnified architecture for 2, 3, 4, 5, and 7‐point DFTs based on Winograd Fourier transform algorithm
Author(s) -
Qureshi F.,
Garrido M.,
Gustafsson O.
Publication year - 2013
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2012.0577
Subject(s) - multiplexer , reconfigurability , fast fourier transform , adder , algorithm , computer science , discrete fourier transform (general) , point (geometry) , fourier transform , architecture , power (physics) , split radix fft algorithm , prime factor fft algorithm , parallel computing , arithmetic , computational science , mathematics , multiplexing , fractional fourier transform , fourier analysis , telecommunications , physics , art , mathematical analysis , geometry , quantum mechanics , visual arts , latency (audio)
A unified hardware architecture that can be reconfigured to calculate 2, 3, 4, 5, or 7‐point DFTs is presented. The architecture is based on the Winograd Fourier transform algorithm and the complexity is equal to a 7‐point DFT in terms of adders/subtractors and multipliers plus only seven multiplexers introduced to enable reconfigurability. The processing element finds potential use in memory‐based FFTs, where non‐power‐of‐two sizes are required such as in DMB‐T.