Open AccessDNN‐aided read‐voltage threshold optimization for MLC flash memory with finite block length
Author(s) -
Wang Cheng,
Wei Kang,
Kong Lingjun,
Shi Long,
Mei Zhen,
Li Jun,
Cai Kui
Publication year - 2022
Publication title -
iet communications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.355
H-Index - 62
eISSN - 1751-8636
pISSN - 1751-8628
DOI - 10.1049/cmu2.12311
Subject(s) - computer science , low density parity check code , decoding methods , voltage , algorithm , threshold voltage , transistor , electrical engineering , engineering
The error‐correcting performance of multi‐level‐cell (MLC) NAND flash memory is closely related to the block length of error‐correcting codes (ECCs) and log‐likelihood‐ratios of the read‐voltage thresholds. Driven by this issue, this paper optimizes the read‐voltage thresholds for MLC flash memory to improve the decoding performance of ECCs with finite block length. First, through the analysis of channel coding rate and decoding error probability under finite block length, the optimization problem of read‐voltage thresholds to minimize the maximum decoding error probability is formulated. Second, a cross‐iterative search algorithm to optimize read‐voltage thresholds under the perfect knowledge of flash memory channel is developed. However, it is challenging to analytically characterize the voltage distribution under the effect of data retention noise. To address this problem, a deep neural network (DNN)‐aided optimization strategy to optimize the read‐voltage thresholds is developed, where a multi‐layer perception network is employed to learn the relationship between voltage distribution and read‐voltage thresholds. Simulation results show that, compared with the existing schemes, the proposed DNN‐aided read‐voltage threshold optimization strategy with a well‐designed Low Density Parity Check (LDPC) code can not only improve the program‐and‐erase endurance but also reduce the read latency.