Open AccessVLSI Design for High‐Precision Three‐Dimensional Depth Perception Chip
Author(s) -
Chenyang GE,
Huimin YAO,
Yanhui ZHOU,
Pengchao DENG
Publication year - 2021
Publication title -
chinese journal of electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.267
H-Index - 25
eISSN - 2075-5597
pISSN - 1022-4653
DOI - 10.1049/cje.2021.04.009
Subject(s) - very large scale integration , computer science , application specific integrated circuit , preprocessor , chip , artificial intelligence , coding (social sciences) , integrated circuit , computer vision , computer hardware , embedded system , mathematics , operating system , telecommunications , statistics
This paper presents a Very large scale integration (VLSI) design method for Three‐dimensional (3D) depth perception chip based on infrared coding structure light. The primary sub‐modules on the chip contain the speckle pattern preprocessing module, block‐matching disparity estimation, depth mapping and post‐processing. The chip employs pipelining technology, and after Application specific integrated circuit (ASIC) verification, it proves that our chip has more advantages in performance of depth precision (12bits, 1mm @ 1m), image resolution (1280×960), time delay (less than 17ms), range limit (0.4~6m). It also can generate more stable and smooth depth map in real‐time, which can be used in 3D recognition, motion capture or scene perception.