Open AccessA Simple BCH Decoder for NoC Interconnects and SoC Buses
Author(s) -
Tao WU,
Ailin YANG
Publication year - 2021
Publication title -
chinese journal of electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.267
H-Index - 25
eISSN - 2075-5597
pISSN - 1022-4653
DOI - 10.1049/cje.2021.03.007
Subject(s) - bch code , computer science , codec , error detection and correction , overhead (engineering) , network on a chip , soft decision decoder , network packet , decoding methods , system on a chip , chip , parallel computing , embedded system , algorithm , computer hardware , computer network , telecommunications , operating system
Network on a chip (NoC) uses packet‐switched network to implement interconnections in System on chip (SoC). In SoC design, performance and energy efficiency are respectively the first and second priorities, and optimal on‐chip communication should decrease the power consumption and area overhead. In this work, a simplified BCH codec is proposed for reliable communication in NoC and SoC. It performs BCH error corrections without Berlekamp's algorithm, only using reduced syndrome bits to determine error patterns. The error locations can be found by looking up tables, by which the possible errors are directly corrected. Only one matrix product and one ROM access are required in the BCH decoder. The proposed (20, 8, 2) and (31, 16, 3) decoders in the paper can be easily applied for error corrections of interconnects and buses for NoC and SoC. It is also beneficial to correct data lines without length definition and control lines without storage.