Open AccessA 16‐bit, ±10‐V Input Range SAR ADC with a 5‐V Supply Voltage and Mixed‐Signal Nonlinearity Calibration
Author(s) -
LUO Hongrui,
ZHAO Xianlong,
JIAO Zihao,
ZHANG Jie,
WANG Xiaofei,
ZHANG Ruizhi,
ZHANG Hong
Publication year - 2022
Publication title -
chinese journal of electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.267
H-Index - 25
eISSN - 2075-5597
pISSN - 1022-4653
DOI - 10.1049/cje.2021.00.057
Subject(s) - successive approximation adc , integral nonlinearity , voltage reference , flash adc , linearity , voltage , calibration , spurious free dynamic range , differential nonlinearity , dynamic range , analog front end , analog to digital converter , electronic engineering , signal (programming language) , cmos , digital to analog converter , analog signal , integrating adc , computer science , capacitor , electrical engineering , physics , engineering , converters , digital signal processing , quantum mechanics , ćuk converter , programming language
This paper presents a high‐precision, successive approximation register (SAR) analog‐to‐digital converter (ADC) with resistive analog front‐end for low‐voltage and wide input range applications. To suppress the serious nonlinearity brought by the voltage coefficients of analog front‐end without deteriorating differential nonlinearity performance, a mixed‐signal calibration scheme based on piecewise‐linear method with calibration digital‐to‐analog converter is proposed. A compensation current is designed to sink or source from the reference to keep it independent of input signal, which greatly improves the linearity performance. Fabricated in a 0.5‐ μ m CMOS process, the proposed ADC achieves 88‐dB signal‐to‐noise‐and‐distortion ratio and 103‐dB spurious free dynamic range with 5‐V supply voltage and 2.5‐V reference voltage, and the total power consumption is 37.5 mW.