Open AccessA 16‐bit Hybrid ADC with Circular‐Adder‐Based Counting for 15μm Pitch 640×512 LWIR FPAs
Author(s) -
Huang Zhaofeng,
Zhu Yajun,
Lu Wengao,
Niu Yuze,
Zhang Shengdong,
Chen Zhongjian
Publication year - 2020
Publication title -
chinese journal of electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.267
H-Index - 25
eISSN - 2075-5597
pISSN - 1022-4653
DOI - 10.1049/cje.2020.01.006
Subject(s) - adder , cmos , pixel , analog to digital converter , quantization (signal processing) , linearity , computer science , effective number of bits , electronic engineering , integral nonlinearity , materials science , computer hardware , voltage , electrical engineering , optoelectronics , engineering , converters , algorithm , artificial intelligence
A hybrid Analog to digital converter (ADC) is presented for long‐wave infrared focal plane arrays. A two‐stage quantization structure is applied in the folding integration process, which results in better chargehandling capacity and higher linearity compared with conventional designs while using fewer transistors at the pixel level. By employing a circular‐adder‐based counting structure with 3T dynamic memory cells, hardware consumption can be reduced. A pixel circuit of pitch 15μm has been designed using the 0.18mm Complementary metal‐oxide‐semiconductor (CMOS) process. The power consumption of the pixel‐level ADC is 0.214μW, and the charge‐handling capacity is 1Ge ‐ . Simulation results demonstrate a signal‐to‐noise ratio of 90dB and a nonlinearity of 0.11%.