Open AccessAn In‐Memory‐Computing Design of Multiplier Based on Multilevel‐Cell of Resistance Switching Random Access Memory
Author(s) -
Dai Lan,
Guo Hong,
Lin Qipeng,
Xia Yongxin,
Zhang Xiaobo,
Zhang Feng,
FAN Dongyu
Publication year - 2018
Publication title -
chinese journal of electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.267
H-Index - 25
eISSN - 2075-5597
pISSN - 1022-4653
DOI - 10.1049/cje.2018.08.006
Subject(s) - computer science , multiplier (economics) , parallel computing , non volatile memory , random access memory , computer hardware , economics , macroeconomics
Due to the Von Neumann bottleneck, in‐memory‐computing, as a new architecture, has drawn considerable attention and is becoming an candidate of next generation electronics system. It presents an inmemory‐computing approach for multiplier design based on Multilevel‐cell (MLC) of Resistive random access memories (RRAMs). The paper proposes a Look‐up‐table (LUT) operations to optimize the speed, area and power of the multiplier circuits. The proposed MLC function of RRAM revealed that RRAM could have a multilevel stable resistance by adjusting the operating voltage. The simulation results show that, taking a 16‐bits multiplier as an example, the circuits of this paper has a calculation speed thatis increased by 35.7 percent and an area that is decreased by 14 percent under the similar power consumption conditions when compared with other traditional 16‐bits multiplier.