Open AccessA Performance Driven Lot Merging Method with Closed Loop Optimization for Semiconductor Wafer Fabrication
Author(s) -
Cao Zhengcai,
Huang Zhexiao,
Liu Min
Publication year - 2017
Publication title -
chinese journal of electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.267
H-Index - 25
eISSN - 2075-5597
pISSN - 1022-4653
DOI - 10.1049/cje.2017.08.019
Subject(s) - wafer , wafer fabrication , fabrication , semiconductor , semiconductor device fabrication , loop (graph theory) , computer science , closed loop , optoelectronics , materials science , process engineering , electronic engineering , mathematics , control engineering , engineering , medicine , alternative medicine , pathology , combinatorics
This paper deals with lot merging problem in semiconductor wafer fabrication system. There is the possibility to merge two or more partial lots into single lot if their subsequent process routes are the same, an improved lot merging method is presented by grouping lots belonging to different orders. Based on job information extracted from the buffers, several bin packing and knapsack solving algorithms are used to determine which lots should be merged. An iterative improvement procedure is introduced for optimizing merging strategy through a heuristic algorithm with resetting the ready time of critical lots. The closed loop structure with global revision factor is built for minimizing the impact of uncertain events while balancing the different orders processing progress. Applied to a simulation semiconductor manufacturing fab, the proposed algorithm can reduce cycle time and tardiness compared with other methods currently.